PRINCIPAL R&D/PRODUCT DVL ENGINEER (SI IO)

At TE, you will unleash your potential working with people from diverse backgrounds and industries to create a safer, sustainable and more connected world. 

Job Overview

Leads engineering in the development and start-up of one or more products.

Job Requirements

Responsibilities:

    • Drive SI design, simulation, and validation for next-gen high-speed interconnects (112G/224G PAM4, PCIe Gen6/7, Co-Packaged, and Near Package) through the product development cycle.
    • Conducting SI COE analysis, including
      • Performing signal integrity simulations and analysis for high-speed interconnect product development. This includes determining the correct simulation methodology and setup to use, as well as a good understanding of the criteria for each interface.
      • Modeling the connector with the consideration of manufacture impact and application impact.
      • Providing solutions to the SI challenges. This includes identifying the problems, making research plans, developing new technologies, and training and sharing the findings with the SI community.
    • Develop novel interconnect solutions by optimizing mating interfaces, lead frames, and PCB transitions for resonance-free, low-loss performance.
    • Enhance bulk cable design & termination techniques to minimize skew, impedance mismatches, and signal degradation.
    • Advance high-frequency testing methodologies beyond 67 GHz with innovative non-PCB-based test fixtures.
    • Utilize AI & big data analytics for predictive SI modeling, auto-routing, and performance optimization.
    • Optimize material selection & electromagnetic design to improve noise isolation, signal integrity, and high-frequency response.
    • Collaborate with NPD teams & industry partners to influence SI strategies, technology roadmaps, and next-gen product designs.

What your background should look like

Required Skills/Experience:

  • Bachelor’s degree in Electrical Engineering or equivalent amount of experience.
  • Minimum of 10+ years of work experience in a signal integrity engineering role.
  • Minimum of 8+ years of work experience in connector development - Experience with interconnect design or experience with connector &/or cable/cable assembly design (high-speed twinax cables, direct attach copper (DAC) cables)
  • Demonstrated experience using Signal integrity analysis tools (Agilent ADS, Ansys HFSS or equivalent, 3D modeling tools) and testing equipment (including VNA, TDR, and BERT).
  • A solid understanding of statistical analysis and AI training.
  • A solid understanding of electromagnetic theory and electrical circuit behavior
  • Strong analytical capabilities to interpret simulation and lab data to identify issues and provide solutions to fix identified problems. 
  • Strong understanding of printed circuit board design, fabrication, and assembly. 
  • Familiar with material, manufacturing process, and manufacture inspection.
  • Familiar with at least one programming language, such as Matlab, Python, C++, VB, etc
  • Excellent presentation, verbal, and written communication skills with an ability to clearly communicate technical concepts to diverse audiences
  • Ability to work in a global environment – able to accommodate varying time zones, fluent in English (verbal/written), able to collaborate with individuals across geographies
  • The individual must be highly motivated, a quick learner, and able to work independently

 

 Nice to have Skills/Experience:

  • Doctor’s degree a PLUS
  • Printed circuit board design (proficient in Altium a PLUS), fabrication and assembly (AutoCAD)
  • Signal conditioning techniques (equalization, amplification)
  • Six Sigma methodologies or other strong data analytics background a PLUS.
  • Experience in project leadership, especially as it applies to design, development & manufacturing teams
  • Direct customer design and support experience
  • Design experience with data center compute equipment like servers, switches, routers, storage, antenna, RF front end, or similar systems.

Competencies

SET : Strategy, Execution, Talent (for managers)
Location: 

SHANGHAI, SH, CN, 200233

City:  SHANGHAI
State:  SH
Country/Region:  CN
Travel:  10% to 25%
Requisition ID:  140593
Alternative Locations: 
Function:  Engineering & Technology


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